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Enabling a solution for on-device and edge AI processing is about more than providing raw TOPS in an SoC. In the fast-evolving world of AI, solutions must provide both high performance and high utilization while handling many more “irregular” operations and not just matrix multiplies (transformers, LSTM, etc.), do so within a low-power and small-area profile with minimal accesses to memory, and be easy to use by developers for the networks of today and of the future.

 

In this presentation, we will discuss Cadence’s AI IP products enabling ultra-low-energy, battery-powered devices up to high-end applications requiring many hundreds of TOPs, supported by powerful software tools that enable a no-code environment for mapping networks to target executables.

Author:

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems
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Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

Every electronic system you know is either going to get smarter or get replaced. AI is allowing us to solve a new set of problems just recently thought of as impossible. The challenge that we have is to make AI work, not just in the data center, but in all the systems we use and interact with daily. These systems vary from a Falcon Heavy Rocket to a smart contact lens. Some have kilowatts of power available, others not even a microwatt. The AI systems we deliver must meet a vast range of requirements and work in all kinds of environments.   

 

Because AI is computationally very complex, using an average off-the-shelf MPU just isn’t going to get the job done. Russell Klein will describe how you can design the next generation of intelligent systems to surpass these challenges.  

 

At the same time, these systems are often placed in situations where they must work all the time, with no disruptions in service. Ankur Gupta will describe how you can use embedded analytics to design AI systems at the edge that operate reliably, safely, and securely.  

Author:

Ankur Gupta

Senior Vice President and General Manager
Siemens EDA

Ankur Gupta is Senior Vice President and General Manager of Digital Design Creation at Siemens EDA. This includes Test, Embedded Analytics, Digital IC design, Power Optimization, and Power Integrity Analysis. Formerly he was head of Product Management and Applications at Ansys, Semiconductor and Head of Applications Engineering for Digital Implementation & Signoff at Cadence Design Systems.

Ankur has 20+ years of experience in EDA, working on some of the industry’s most innovative Test, Digital Design, Implementation and Signoff products. He holds a Master’s Degree in Electrical and Computer Engineering, from Iowa State University.

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Ankur Gupta

Senior Vice President and General Manager
Siemens EDA

Ankur Gupta is Senior Vice President and General Manager of Digital Design Creation at Siemens EDA. This includes Test, Embedded Analytics, Digital IC design, Power Optimization, and Power Integrity Analysis. Formerly he was head of Product Management and Applications at Ansys, Semiconductor and Head of Applications Engineering for Digital Implementation & Signoff at Cadence Design Systems.

Ankur has 20+ years of experience in EDA, working on some of the industry’s most innovative Test, Digital Design, Implementation and Signoff products. He holds a Master’s Degree in Electrical and Computer Engineering, from Iowa State University.

Author:

Russell Klein

Program Director, CSD Division
Siemens

Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor. 

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Russell Klein

Program Director, CSD Division
Siemens

Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor. 

Abstract coming soon...

Author:

Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

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Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

Author:

Petr Lapukhov

Network Engineer
NVIDIA

Petr Lapukhov is a Network Engineer at Meta. He has 20+ years in the networking industry, designing and operating large scale networks. He has a depth of experience in developing and operating software for network control and monitoring. His past experience includes CCIE/CCDE training and UNIX system administration.

... read more

Petr Lapukhov

Network Engineer
NVIDIA

Petr Lapukhov is a Network Engineer at Meta. He has 20+ years in the networking industry, designing and operating large scale networks. He has a depth of experience in developing and operating software for network control and monitoring. His past experience includes CCIE/CCDE training and UNIX system administration.

 

Petr Lapukhov

Network Engineer
NVIDIA

Petr Lapukhov is a Network Engineer at Meta. He has 20+ years in the networking industry, designing and operating large scale networks. He has a depth of experience in developing and operating software for network control and monitoring. His past experience includes CCIE/CCDE training and UNIX system administration.

Read full bio

Petr Lapukhov

Network Engineer
NVIDIA

Petr Lapukhov

Network Engineer
NVIDIA

Petr Lapukhov is a Network Engineer at Meta. He has 20+ years in the networking industry, designing and operating large scale networks. He has a depth of experience in developing and operating software for network control and monitoring. His past experience includes CCIE/CCDE training and UNIX system administration.

Join this moderated roundtable discussion group of 10-20 attendees focusing on AI hardware & systems design.

There will be several moderators per topic area to allow for multiple tables and questions will be prepared in advance. Each group will be multidisciplinary with representation from across the tech stack. Attendees who have registered for the event will be able to sign up for the roundtable discussion groups closer to the event, or via an AI Hardware & Edge AI Summit sales representative.

The subtopics to be discussed will include:

- Tackling power consumption for AI hardware
- Memory bandwidth and capacity challenges and solutions
- AI hardware & systems co-design
- System software engineering challenges for novel AI hardware

Join this moderated roundtable discussion group of 10-20 attendees focusing on selecting ML training platforms for specific use cases. 

There will be several moderators per topic area to allow for multiple tables and questions will be prepared in advance. Each group will be multidisciplinary with representation from across the tech stack. Attendees who have registered for the event will be able to sign up for the roundtable discussion groups closer to the event, or via an AI Hardware & Edge AI Summit sales representative.

The subtopics to be discussed will include:

- GPUs vs ASICS vs commodity hardware (i.e. software-accelerated CPUs)
- Considerations for efficient training of training large language models
- Fitting workloads to training hardware - overcoming issues with memory etc.
- Software considerations for novel AI hardware training platforms

In his forthcoming keynote, Lip Bu Tan delves into the transformative impact of Generative AI on today's rapidly evolving intelligent systems. This critical conversation sheds light on the symbiotic relationship between AI semiconductors and systemic hardware growth drivers, showcasing how they are steering the future of purpose-built intelligent systems.

 

As we navigate this unprecedented era of technological advancement, Mr. Tan will explore how Generative AI platforms are accelerating design productivity and enabling innovative AI chip design tools, and define what’s needed to deliver a full generative AI system stack. The keynote will also touch upon the extension of these advancements, highlighting how computational software initially developed for AI can be adapted and applied to other domains, thereby broadening the impact and utility of intelligent systems.

 

Don't miss this enlightening session that promises to redefine our understanding of AI's role in shaping intelligent systems and expanding the frontiers of what's possible across multiple sectors.

Author:

Lip-Bu Tan

CEO
Intel

Lip-Bu Tan is chief executive officer of Intel Corporation and serves on the company’s board of directors. He was appointed to his position in March 2025.

Tan is an accomplished executive with more than two decades of semiconductor and software experience and deep relationships across the technology ecosystem. He has received several accolades for his significant contributions to the industry, including the 2022 Robert N. Noyce Award, the Semiconductor Industry Association’s highest honor, and was named one of Forbes’ Top 50 Venture Capitalists.

Tan previously served as chief executive officer of Cadence Design Systems Inc. and was also a member of its board of directors. During his 12 years as Cadence’s chief executive officer, he led a reinvention of the company and drove a cultural transformation centered on customer-centric innovation that enabled Cadence to more than double its revenue, expand operating margins and significantly outperform the market.

Tan is a founding managing partner of Walden Catalyst Ventures and chairman of Walden International, a leading venture capital firm. He has also served on the boards of public companies Credo Technology Group and Schneider Electric.

Tan holds a Bachelor of Science in physics from Nanyang Technological University in Singapore, a Master of Science in nuclear engineering from the Massachusetts Institute of Technology and an MBA from the University of San Francisco.

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Lip-Bu Tan

CEO
Intel

Lip-Bu Tan is chief executive officer of Intel Corporation and serves on the company’s board of directors. He was appointed to his position in March 2025.

Tan is an accomplished executive with more than two decades of semiconductor and software experience and deep relationships across the technology ecosystem. He has received several accolades for his significant contributions to the industry, including the 2022 Robert N. Noyce Award, the Semiconductor Industry Association’s highest honor, and was named one of Forbes’ Top 50 Venture Capitalists.

Tan previously served as chief executive officer of Cadence Design Systems Inc. and was also a member of its board of directors. During his 12 years as Cadence’s chief executive officer, he led a reinvention of the company and drove a cultural transformation centered on customer-centric innovation that enabled Cadence to more than double its revenue, expand operating margins and significantly outperform the market.

Tan is a founding managing partner of Walden Catalyst Ventures and chairman of Walden International, a leading venture capital firm. He has also served on the boards of public companies Credo Technology Group and Schneider Electric.

Tan holds a Bachelor of Science in physics from Nanyang Technological University in Singapore, a Master of Science in nuclear engineering from the Massachusetts Institute of Technology and an MBA from the University of San Francisco.

 

Ginny Siller

Director Government Affairs
Animal Health Institute

Ginny Siller

Director Government Affairs
Animal Health Institute

Ginny Siller

Director Government Affairs
Animal Health Institute

Abstract coming soon...

Moderator

Author:

Sally Ward-Foxton

Senior Reporter
EETimes

Sally Ward-Foxton has been writing about the electronics industry for more than a decade. As a freelance journalist she has published articles in EE Times, Electronic Design Europe, Microwaves & RF, ECN, Electronic Specifier: Design, IoT Embedded Systems, Electropages, Components in Electronics and many more. She also supplies technical writing and ghostwriting services to several of Europe's leading PR agencies. She holds a Masters' degree in Electrical and Electronic Engineering from the University of Cambridge, UK.

... read more

Sally Ward-Foxton

Senior Reporter
EETimes

Sally Ward-Foxton has been writing about the electronics industry for more than a decade. As a freelance journalist she has published articles in EE Times, Electronic Design Europe, Microwaves & RF, ECN, Electronic Specifier: Design, IoT Embedded Systems, Electropages, Components in Electronics and many more. She also supplies technical writing and ghostwriting services to several of Europe's leading PR agencies. She holds a Masters' degree in Electrical and Electronic Engineering from the University of Cambridge, UK.

Panellists:

Author:

Jim Keller

CEO
Tenstorrent

Jim Keller is the CEO of Tenstorrent and a veteran hardware engineer. Prior to joining Tenstorrent, he served two years as Senior Vice President of Intel's Silicon Engineering Group. He has held roles as Tesla's Vice President of Autopilot and Low Voltage Hardware, Corporate Vice President and Chief Cores Architect at AMD, and Vice President of Engineering and Chief Architect at P.A. Semi, which was acquired by Apple Inc. Jim has led multiple successful silicon designs over the decades, from the DEC Alpha processors, to AMD K7/K8/K12, HyperTransport and the AMD Zen family, the Apple A4/A5 processors, and Tesla's self-driving car chip.

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Jim Keller

CEO
Tenstorrent

Jim Keller is the CEO of Tenstorrent and a veteran hardware engineer. Prior to joining Tenstorrent, he served two years as Senior Vice President of Intel's Silicon Engineering Group. He has held roles as Tesla's Vice President of Autopilot and Low Voltage Hardware, Corporate Vice President and Chief Cores Architect at AMD, and Vice President of Engineering and Chief Architect at P.A. Semi, which was acquired by Apple Inc. Jim has led multiple successful silicon designs over the decades, from the DEC Alpha processors, to AMD K7/K8/K12, HyperTransport and the AMD Zen family, the Apple A4/A5 processors, and Tesla's self-driving car chip.

Author:

Raja Koduri

Board Member
Tenstorrent
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Raja Koduri

Board Member
Tenstorrent

Author:

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

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Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Author:

Laurent Moll

Chief Operating Officer
Arteris

Dr. Laurent Moll most recently served as Vice President of Engineering at Qualcomm where he led a 500-person team creating infrastructure IP for Qualcomm’s chips, including NoC interconnects, memory subsystems, cache coherency subsystems and more. Laurent has led a storied career for over two decades, performing key technical roles at industry leaders such as Digital Equipment Corporation, Compaq Computer Corporation, SiByte, Broadcom, Montalvo Systems and NVIDIA. Prior to his nearly 8-year tenure at Qualcomm, he was the Chief Technology Officer at Arteris Inc, a predecessor company of Arteris. Throughout his career, he has played an influential role in inventing the system-on-chip architectures, IP subsystems, and methodologies that are today the foundation of modern semiconductor design. Laurent earned his PhD in Computer Science at École Polytechnique and holds over 60 patents on various aspects of SoC technology.

 

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Laurent Moll

Chief Operating Officer
Arteris

Dr. Laurent Moll most recently served as Vice President of Engineering at Qualcomm where he led a 500-person team creating infrastructure IP for Qualcomm’s chips, including NoC interconnects, memory subsystems, cache coherency subsystems and more. Laurent has led a storied career for over two decades, performing key technical roles at industry leaders such as Digital Equipment Corporation, Compaq Computer Corporation, SiByte, Broadcom, Montalvo Systems and NVIDIA. Prior to his nearly 8-year tenure at Qualcomm, he was the Chief Technology Officer at Arteris Inc, a predecessor company of Arteris. Throughout his career, he has played an influential role in inventing the system-on-chip architectures, IP subsystems, and methodologies that are today the foundation of modern semiconductor design. Laurent earned his PhD in Computer Science at École Polytechnique and holds over 60 patents on various aspects of SoC technology.

 

AI and security workloads are clearly driving next-generation SoC architecture innovations. These architectures need higher performance, and more memory per processing element as technology process nodes advance.  However, memories are scaling at smaller rates than the processing elements but the workloads are demanding more memory per processing element leading to a memory wall -- there must be technology disruptions.  Off-chip memory offers performance gains, but AI workloads require more efficient and higher density memories per processing element. One clear solution has been multi-die systems, leveraging more on-chip memories at higher bandwidths and improved densities.  This presentation will explore these memory and IO innovations and will showcase several real-world case studies on the development of multi-die systems to meet the AI performance and memory challenges.

 

Author:

Ron Lowman

AI Strategic Marketing Manager
Synopsys

Ron Lowman joined Synopsys in 2014 and is currently the AI Strategic Marketing Manager for the Solutions Group. Ron is responsible for driving Synopsys’ Artificial Intelligence market IP initiatives, including strategic business and market trend analysis.

Prior to joining Synopsys, Lowman spent 16 years at Motorola/Freescale in Controls Engineering, Automotive Product & Test Engineering, Product Management, Business Development, Operations, and Strategy Roles.

Ron holds a Bachelor of Science in Electrical Engineering from Colorado School of Mines and an MBA from the University of Texas in Austin.

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Ron Lowman

AI Strategic Marketing Manager
Synopsys

Ron Lowman joined Synopsys in 2014 and is currently the AI Strategic Marketing Manager for the Solutions Group. Ron is responsible for driving Synopsys’ Artificial Intelligence market IP initiatives, including strategic business and market trend analysis.

Prior to joining Synopsys, Lowman spent 16 years at Motorola/Freescale in Controls Engineering, Automotive Product & Test Engineering, Product Management, Business Development, Operations, and Strategy Roles.

Ron holds a Bachelor of Science in Electrical Engineering from Colorado School of Mines and an MBA from the University of Texas in Austin.